Phase 3 is the AGC circuit. It is an extremely interesting circuit. The JFETs are operated in the "voltage controlled resistor" region. There are also a couple of capacitors that determine the AGC "attack" time.

The problems described in the "Electronics of Radio" book needs a function generator, which I unfortunately do not have. I have been wiring up a DDS based siggen, but it is certainly not in a position to be used.. I need a way to control amplitude for these experiments.

Also, I do not have J309 JFETs with me. Instead I have J310 with me.. I will have to read the data sheet closely to determine whether it poses a problem for this application. My guess is that it is most probably not a problem. But it needs to be ascertained.

I plan to play a bit with LTSpice and simulate the circuit as best as I can and post the results here before I start to actually build it.

edit: May 22: I looked around for old HP function/signal generator. They are bulky, expensive.. So, I am leaning towards building a DDS based generator into a big piece of veroboard. It has been proven on the breadboard. For amplitude control, I may use some kind of a step attenuator for now. I will later add an external amplifier to the DDS..